Sometimes a logic analyzer is just what you need, especially if you’re reverse engineering wire protocols. I actually own an actual logic analyzer, but after spending some time debugging have determined it to have failed/be faulty. So I got to thinking that a Nucleo board can be pretty fast, not FPGA fast, but fast enough for sampling most of the protocols I’ve ended up dealing with, so I decided to give it a try.
I was initially thinking about how I would implement this, but I didn’t really want to deal with all the tech required to nicely display signals on my computer. Of course this is the point where one must remember to check if a wheel exists before reinventing it.
What I found was LogicalNucleo, an existing project to turn a Nucleo F401RE into a SUMP compatible logic analyzer. SUMP is a logic analyzer protocol used for logic analyzers such as the OLS, better yet, LogicSniffer is an existing desktop application to handle the user interface, display and decoding of signals! Only problem is I don’t have a Nucleo F401RE. What I do have is the slightly faster, and slightly larger SRAM Nucleo F411RE. So I decided to port it over.
This was actually a relatively simple, albeit tiresome process as the main task was tuning large sequences of inline asm NOP’s used for timing at the fastest timescales. I’m sad to say this was mostly a trial and error process, using the existing test functionality to generate known period PWM signals to calibrate against. I used some relative ratios from the clock speeds and extrapolated the number of clock cycles used for actual computation to get in the ballpark, but then spent a fair while getting them as close as I could by hand. I additionally doubled the buffer size to use the increased SRAM on the 411, and doubled the serial rate (fastest I could get it to be stable with my setup) to improve the transfer speed of captured signals to the computer. I also put together a config file for Logic Sniffer for this board, that mainly just restricts the options to those that are actually implemented so you don’t select unsupported sample rates, etc. It also allows the handy feature of autodetecting the board though. Grab it here.
Sadly I am unable to use my new logic analyzer for the intended project at this time, as the signals aren’t quite at the right voltage. I haven’t gone through the checking to see if the pins for this particular Nucleo would handle input up to 5 volts (but I don’t think it does), but in this particular case I’m working on signals closer to 2.8 volts, not quite high enough to trigger the Nucleo’s inputs. I’ve ordered a couple of logic level converters to allow me to use this for a range of voltages.
My version is published here. There are still some things that may be able to be substantially improved for using Nucleo boards as logic analyzers. I may try to play around with some alternate approaches to try and improve usabilty and performance of Nucleo’s as logic analyzers. There’s also a company doing this sort of thing commercially called SysProgs(no endorsement).